For efficient data storage it is advantageous to reduce the amount of data in the storage and to reproduce a series or sequence of signals from only two consecutively stored signals or storage values. In this way, storage space can be saved and/or data to be stored can be compressed. For specific applications, for instance with wearable or mobile electronic devices, such like mobile phones or wrist watches there might be a demand for storing data representing sound or music at a comparatively low sampling rate. When reading the data from the memory and for reproducing the sound or music from the stored data a hardware implemented interpolation of the stored signals is generally required.
There exists solutions for digital interpolators that make use of a cascade of finite response filters (FIR), e.g. in order to implement an interpolation from 32 kHz to 256 kHz. Such a cascade of FIR filters requires a comparatively large amount of gates or memory blocks, which in turn may cover a major portion of the area of a respective integrated circuit (IC).
An interpolation filter is also known in view of the patent application EP 0 658 979 A2 and the patent U.S. Pat. No. 5,835,390.
The patent application US 2010/0135368 A1 describes an apparatus able to perform an interpolation of an input sample stream. For that the interpolating mechanism comprises an up-sampler structure, which includes a linear interpolator. The up-sampler circuit comprises a differentiator, a linear interpolator and an integrator for providing an output interpolated signal having a frequency greater than the frequency of the input signal.